Cronologic Ndigo Crate Podręcznik Użytkownika

Revision 1.1 as of 2013-11-13Firmware 0 (build 3795), Driver v0.9.22cronologic GmbH & Co. KGNdigo250M-14Ndigo125M-14User Guide

+-450MHzoffsetFigure 2.4: Input circuit for each of the four analog channels.2.2.2 Analog InputsThe analog inputs of the ADC are single ended LEMO00 c

6.4.3. This feature is especially useful for highly asymmetric signals, such as pulses from TOF+0.5Vanalog_offset[i] = 0V-0.5 V+0.5Vanalog_offset[i] =

analog_offset[4]-1,0V1,0VFigure 2.8: For TRIGGER and GATE negative thresholds can be set to support negative signalssuch as 16mA NIM.TDC on Input TRIG

2.4 Ndigo250M-14 FunctionalityThe analog input signal is quantized to 14 bits. However, the board always scales and offsetsthe data to 16 bit signed da

2.4.2 Trigger BlocksThe Ndigo250M-14 records analog wave forms using zero suppression. Whenever a relevantwaveform is detected, data is written to an

precursor = 6 length = 12total length = 19thresholdFigure 2.10: Parameters for edge triggeringprecursor = 6 length = 6total length = 21thresholdFigure

risingsample datathresholdZ-1edgetrigger 1risingthresholdZ-1edgetrigger 2Figure 2.12: From the ADC inputs, a trigger unit creates an input flag for the

A B C D trigger_ block[0] trigger_ block[1] trigger_ block[2] trigger_ block[3] Gates bus[0] bus[1] bus[2] bus[3] to cable sync time stamp channel fun

2.4.3 Gating BlocksFigure 2.15: Gating Blocks: Each gating block can use an arbitrary combination of inputs totrigger its state machine. The outputs c

Figure 2.16 shows the functionality of the gate timing and delay unit. Active gate time ismarked in green.TriggerGateGate StartGate StopFigure 2.16: G

its output after the specified delay.To send this pulse to the trigger block, the gating block must be enabled in the trigger block’sAND matrix and the

2.5 Multiple Ndigo boards synchronizationUsing several Ndigo devices in applications that use more channels than a single board canprovide requires sy

2.5.1 Calibration Procedure1. Make sure the “Automode” is selected.2. Record the calibration histograms by pressing “Record histograms”. The program w

Figure 2.18: Histogram for the case the delay value for the board is not set correctly. Pleasenote: the lower panel might differ from board to board, w

2.5.2 Synchronizing with an HPTDC8-PCIThe Ndigo250M-14 does not support synchronization with an HPTDC8-PCI.cronologic GmbH & Co. KG 20 Ndigo250M-1

2.6 Performing a firmware updateAfter installing the Ndigo device driver, a firmware update tool is available. By choosing“NdigoFirmwareGUI.exe” a firmwa

information shown in the upper half of the application window does not change right afterflashing a new firmware.2.6.1 Calibrating the TDCAfter each upd

tion data on the card.6. Calibration done!The card can only be successfully calibrated if:First Bin is in the range of 4 to 16Empty Bins is less than

cronologic GmbH & Co. KG 24 Ndigo250M-14 User Guide

3 Driver Programming APIThe API is a DLL with C linkage. There also exists a .Net wrapper.The functions provided by the DLL are declared in Ndigo250M

Contents1 Introduction 11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Hardware 32.1 Installing the

3.2 Initializationint ndigo250m count devices(int *error code, char **error message)Return the number of boards that are supported by this driver in t

ndigo bool t is slaveData acquisition of this board is controlled by the master board.int sync periodPeriod of the multicard sync pulse. Ignored for s

3.3 Status Information3.3.1 Functions for Information RetrievalThe driver provides functions to retrieve detailed information on the type of board, it

A change in the first digit generally requires a recompilation of user applications. Change inthe second digit denote significant improvements or change

3.3.3 Structure ndigo param infoint sizeThe number of bytes occupied by the structure.int versionA version number that is increased when the definition

Alert flags from the system monitor and temperature sensor. Bits 0 to 3 are measured by thesystem monitor of the FPGA. Bits 4 and 5 are provided by an

3.4 ConfigurationThe device is configured with a configuration structure. The user should first obtain a structurethat contains the default settings of th

Configuration of the external trigger sources. Threshold is ignored for entries 8 and above.The trigger indexes refer to the entry in the trigger array

T = 1 + M + [1...2N] (3.1)clock cycles.0 ≤ M < 232(3.2)0 ≤ N < 32 (3.3)There is no enable or reset as the usage of this trigger can be configured

For trigger indices NDIGO TRIGGER AUTO and NDIGO TRIGGER ONE this is ignored.For trigger indices NDIGO TRIGGER TDC PE to NDIGO TRIGGER BUS3 PE this mu

Contents3.4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.4.1 Structure ndigo250m configuration . . . .

#define NDIGO TRIGGER SOURCE GATE 0x00000200#define NDIGO TRIGGER SOURCE BUS0 0x00000400#define NDIGO TRIGGER SOURCE BUS1 0x00000800#define NDIGO TRIGGER

created.NOT IMPLEMENTEDndigo bool t reserved1Defaults to false. Do not change.int startThe number of samples from the first input signal seen in the id

3.4.6 Run Time Controlint ndigo start capture(ndigo device *device)int ndigo pause capture(ndigo device *device)int ndigo continue capture(ndigo devic

3.5 Readoutint ndigo250m read(ndigo device *device, ndigo250m read in *in, ndigo250m read out *out)For each DMA channel returns a pointer to an array

separately for each channel.cronologic GmbH & Co. KG 40 Ndigo250M-14 User Guide

3.6 Other Functions3.6.1 LED controlThere are six LEDs on the front panel. The intensity of the red and green part can be set from0 to 255. There is n

cronologic GmbH & Co. KG 42 Ndigo250M-14 User Guide

4 Packet Format4.0.2 Output Structure ndigo packetunsigned char channel0 to 3 for the ADC input channels, 4 for the TDC, 5 for the timestamp channel.u

Number of 64-bit elements (each containing 4 samples) in the data array if type < 128.If type = 128 this is the pattern of trigger sources that whe

5 C Example1 #i n c l u d e ” N d i g o i n t e r f a c e . h”2 #i n c l u d e <s t d i o . h>3 #i n c l u d e <s t d l i b . h>45 i n t m

1 IntroductionThe Ndigo250M and Ndigo125M are digitizer and transient recorders designed to sample rela-tively shorts pulses in rapid repetition. They

3940 c o n f i g . t r i g g e r b l o c k [ 0 ] . s o u r c e s = NDIGO TRIGGER SOURCE A0 ;41 c o n f i g . t r i g g e r b l o c k [ 0 ] . l e n g t

85 pa c k et = n e x t p a c k e t ;86 co unt++;87 }88 }89 }90 n d i g o c l o s e ( ndgo ) ;91 r e t u r n 0 ;92 }cronologic GmbH & Co. KG 47 Ndi

cronologic GmbH & Co. KG 48 Ndigo250M-14 User Guide

6 Technical Data6.1 Operating Conditions6.1.1 Environmental Conditions for OperationThe board is designed to be operated under the following condition

6.3 TDC CharacteristicsSymbol Parameter Min Typ Max UnitsBINTDCTDC bin size psINLTDCTDC integral nonlinearityInput Pulse Width 3.3 nsInput Pulse Spaci

Symbol Parameter Min Typ Max UnitsVDthdiscrimination threshold -1.25 1.25 VVdnrecommended amplitude for negative pulses -0.1 - VDth2VDth1.25 - VDthVVd

6.5 Information Required by DIN EN 61010-16.5.1 ManufacturerThe Ndigo250M-14 is a product of:cronologic GmbH & Co. KGJahnstraße 4960318 FrankfurtH

6.5.4 Environmental ConditionsRefer to the sections on Environmenal Conditions on page 496.5.5 InputsThe analog inputs are DC coupled. The inputs have

2 Hardware2.1 Installing the BoardThe Ndigo250M-14 board can be installed in any PCIe slot with eight or more lanes. If the slotelectrically supports

C1C1C1terminationtermination C2 C2 C2Figure 2.1: If several Ndigo boards are connected to work in sync , the boards must be con-nected using a ribbon

2.2 External Inputs and Connectors2.2.1 ConnectorsThe inputs of the Ndigo250M-14 are located on the PCI bracket. Figure 2.3 on page 5 shows thelocatio