Cronologic Ndigo Crate Podręcznik Użytkownika

Revision 0.2.31 as of 2014-10-28Firmware 2 (build 4739), Driver v0.9.39cronologic GmbH & Co. KGNdigo5G-8Ndigo5G-10User Guidecronologic

BC2CDTGC1AFigure 2.3: Schematics of an Ndigo5G board showing inter-board connectors C1 and C2.2.2.2 Analog InputsTC1-1-I3M+Lemo 00 connectoranalog-off

+0,25Vanalog_offset[i] = 0V-0,25V+0,25Vanalog_offset[i] = 0,1V-0,25V0,1VFigure 2.5: Users can add analog offset to the input before sampling+0,25Vanalo

2.3 Extension CardThe Ndigo Extension card provides additional inputs or outputs to the FPGA. It is connectedto the Samtec QSS-025 connector on an Ndi

2.4.1 ADC ModesDepending on board configuration, the analog input signal is quantized to 8 or 10 bits. However,the board always scales and offsets the d

CLK(2.5 GHz)Clock circuit1.25 GHzADC A1.25 GspsADC B1.25 GspsADC C1.25 GspsADC D1.25 GspsAAI, AAIN BAI, BAIN CAI, CAIN DAI, DAINFigure 2.7: ADCs in 4

2.4.2 Zero SuppressionOne of Ndigo 5G’s key features is on-board zero suppression to reduce PCIe bus load. Only datathat passes specifications predefine

precursor + length + 1 cycles of 3.2ns. For level triggering, packet length is data dependent(Figure 2.12 on page 12).Please note that triggering is n

precursor = 6 length = 6total length = 21thresholdFigure 2.12: Parameters for level triggeringprecursor = 1length = 2total length = 4threshold3200 psF

precursor = 1length = 2total length = 4threshold3200 psFigure 2.15: Triggering in 1 channel mode at 16 samples per clock cycle.risingsample datathresh

enable extension input ignore_cable cable syncFigure 2.18: The extension block combines signals from the optional extension board and thesync cable.A

2.4.4 Gating BlocksTriggerFigure 2.20: Gating Blocks: Each gating block can use an arbitrary combination of inputs totrigger its state machine. The ou

TriggerGateGate StartGate StopFigure 2.21: Gate and delay functionality: When a trigger occurs, the gate opens after a setperiod of time (“gate start”

Since the triggers are only connected by OR in the triggerblock logic (see fig. 2.19) they areassigned to one of the gates each and connected with AND

TriggerFigure 2.23: Gating block logic for the AND connection of two triggers.2.4.5 Auto Triggering Function GeneratorSome applications require period

time of the trigger event except for the period monitor. Only one packet is created, no matterhow many trigger sources caused the timestamp channel to

Flashing the values might take up to 10 seconds during which the program might not respond.Important note:If the application reports a “PLL not locked

Figure 2.25: Histogram for the case the delay value for the board is not set correctly. Pleasenote: the lower panel might differ from board to board, w

2.5.2 Synchronizing a Ndgio5G and an HPTDC8-PCIIn order to operate a Ndigo5G in sync with one ore more HPTDC8-PCI boards, a board toboard in -terconne

Contents1 Introduction 11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Hardware 32.1 Installing the

Contents3.5 Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.5.1 Input Structure ndigo read in . . . . .

1 IntroductionThe Ndigo5G is a digitizer and transient recorder designed to sample relatively shorts pulsesin rapid repetition. It produces a stream o

2 Hardware2.1 Installing the BoardThe Ndigo5G board can be installed in any x4 (or higher amount of lanes) PCIe slot. If the slotelectrically supports

C1C1C1terminationtermination C2 C2 C2Figure 2.1: If several Ndigo boards are connected to work in sync , the boards must be connectedusing a ribbon ca